In this paper we initially present two CNTFET models: the first is already proposed by us and the second is the Stanford model, proposing a method to match the output characteristics and transconductance characteristics between these two models. Then we describe a compact noise model, used to simulate the performance of a NOT gate, in order to analyze how the noise sources constitute a significant limitation in the design of circuits based on CNTFET. All simulations are obtained using the programming language Verilog-A on the simulator Advanced Design System (ADS), highlighting the solutions proposed in order to use this software.

Implementation of Noise Effects on CNTFET-based NOT Gate in Verilog-A

Anna Gina Perri
Conceptualization
2022

Abstract

In this paper we initially present two CNTFET models: the first is already proposed by us and the second is the Stanford model, proposing a method to match the output characteristics and transconductance characteristics between these two models. Then we describe a compact noise model, used to simulate the performance of a NOT gate, in order to analyze how the noise sources constitute a significant limitation in the design of circuits based on CNTFET. All simulations are obtained using the programming language Verilog-A on the simulator Advanced Design System (ADS), highlighting the solutions proposed in order to use this software.
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Utilizza questo identificativo per citare o creare un link a questo documento: http://hdl.handle.net/11589/240200
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