Investigating the Effectiveness of H-Bridge in Mitigating Switch Faults of a Single-Phase Five-Level Inverter

The use of multilevel inverters (MLIs) is increasingly popular due to their ability to operate at high power and reduce voltage stress on semiconductor switches compared to conventional inverters. However, the greater number of conducting semiconductor switches in MLIs, coupled with their higher failure rate, can weaken the inverter system. Five-level inverters provide an optimal balance by leveraging MLI benefits without significantly increasing semiconductor devices. This paper defines parameters to evaluate both quantitative and qualitative aspects of three recently proposed fault-tolerant MLI topologies. By scrutinizing these topologies, a generalized redundant leg architecture is proposed. This architecture is adaptable to any five-level MLI topology, whether it requires fault tolerance or already possesses it. The proposed solution, validated through comparative analysis and experiments, demonstrates superior fault tolerance with only one switch conducting from the redundant leg under faulty conditions, outperforming related works.