As is generally known, compared with MOSFETs bipolar transistors provide better performance in terms of small signal transconductance, intrinsic cut-off frequency and noise characteristics, at the cost of a more expensive technology. A good compromise between the low costs proper of standardCMOS technology and the excellent performance typical of bipolardevices can be achieved by using bipolar transistors derived from MOS structures. Naturally suitable models combined with efficient parameter extraction techniques are mandatory to provide designers with reliable simulation tools. Adc parameter extraction procedure for a PNP lateral transistor realized in astandardCMOS technology based on an existing composite circuit model is presented here. The extraction results provide accurate fitting between measured and simulated data for different operating regions without resort to numerical optimization, thus preserving the physical meaning of the extracted parameters and retaining a good correlation with process variations.
|Titolo:||Dc characterization of lateral bipolar devices in standard CMOS technology: a new model for base current partitioning|
|Data di pubblicazione:||1999|
|Digital Object Identifier (DOI):||10.1016/S0038-1101(99)00013-1|
|Appare nelle tipologie:||1.1 Articolo in rivista|