A new technique for a simple and realistic worst case analysis of CMOS circuit structures is presented. This methodology preserves correlation between model paranietcrs and provides results similar to those produced by extensive Monte Carlo simulations, comparing favourably to other traditional worst case tcchniques in terms of result accuracy and computational effort required.
|Titolo:||Fast and Realistic Worst Case Analysis of CMOS Integrated Circuits|
|Data di pubblicazione:||2001|
|Digital Object Identifier (DOI):||http://dx.doi.org/10.1049/el:20010254|
|Appare nelle tipologie:||1.1 Articolo in rivista|