An Approach to the Statistical Analysis of CMOS Integrated Circuits

Deep sub-micron CMOS technologies are characterized by a sensible dispersion in the circuit performances due to the technology process fluctuations. Circuit designers are thus faced with an increasing need for accurate statistical analyses to guarantee the correct circuit operation against these effects. Here we present a technique for a simple and “realistic” estimation of the performance limits of CMOS IC’s which preserves correlation between model parameters and gives more realistic results as compared with existing and commonly used worst case approaches. Moreover a comparative analysis between different worst case techniques has been performed with reference to a few widely used basic circuit structures.