Modelling digital circuits with delays by Stochastic Petri Nets

The analysis of the behaviour of digital circuits, with special reference to signal propagation delays, is performed by means of the Petri Nets (PN) formal model. In particular, concurrent signal changes in the circuit which may give rise to possible functional errors such as races or hazards, are represented by this model. Moreover, the delays, assumed to be random variables with assigned probability distributions and Stochastic Petri Nets (SPN), which are an extension of classical PN's, are employed. By the resulting model, a great flexibility of representation is achieved, matching also the requisites of the particular technology employed. It is also possible to account for time varying inputs both in combinational and sequential circuits, reconvergent fanouts and conflicting events. The algorithm derived from this model allows to obtain a static logic verification of the circuit and exhibits shorter simulation times as compared to those of classical simulators.