We propose a novel CMOS baseline holder circuit, able to keep at a specified value the dc output voltage of typical integrated front-end analog channels coupled to silicon detectors, for both high energy physics and medical imaging applications. The circuit, together with the shaping filter, forms a slow feedback loop. A very low frequency pole is obtained in the feedback path, without using large capacitance values, by exploiting a circuit technique based on the properties of operational transconductance amplifiers. The huge time constant achievable with the proposed technique makes this solution suitable to be applied to high-gain front-end circuits, since the stability conditions can be easily fulfilled. Two different non- linearity effects are exploited to limit the baseline shift which occurs at high signal rates. The circuit has been designed in a standard CMOS 0.35μm technology and the first experimental results obtained from different prototypes show the effectiveness of the proposed solution.

A Novel Output Baseline Holder Circuit for CMOS Front-End Analog Channels / Corsi, Francesco; Foresta, M; Marzocca, Cristoforo; Matarrese, Gianvito; Tauro, A.. - (2008), pp. 1476-1481. (Intervento presentato al convegno IEEE Nuclear Science Symposium, 2008, NSS '08 tenutosi a Dresden nel 19-25 October 2008) [10.1109/NSSMIC.2008.4774694].

A Novel Output Baseline Holder Circuit for CMOS Front-End Analog Channels

CORSI, Francesco;MARZOCCA, Cristoforo;MATARRESE, Gianvito;
2008-01-01

Abstract

We propose a novel CMOS baseline holder circuit, able to keep at a specified value the dc output voltage of typical integrated front-end analog channels coupled to silicon detectors, for both high energy physics and medical imaging applications. The circuit, together with the shaping filter, forms a slow feedback loop. A very low frequency pole is obtained in the feedback path, without using large capacitance values, by exploiting a circuit technique based on the properties of operational transconductance amplifiers. The huge time constant achievable with the proposed technique makes this solution suitable to be applied to high-gain front-end circuits, since the stability conditions can be easily fulfilled. Two different non- linearity effects are exploited to limit the baseline shift which occurs at high signal rates. The circuit has been designed in a standard CMOS 0.35μm technology and the first experimental results obtained from different prototypes show the effectiveness of the proposed solution.
2008
IEEE Nuclear Science Symposium, 2008, NSS '08
978-1-4244-2715-4
978-1-4244-2714-7
A Novel Output Baseline Holder Circuit for CMOS Front-End Analog Channels / Corsi, Francesco; Foresta, M; Marzocca, Cristoforo; Matarrese, Gianvito; Tauro, A.. - (2008), pp. 1476-1481. (Intervento presentato al convegno IEEE Nuclear Science Symposium, 2008, NSS '08 tenutosi a Dresden nel 19-25 October 2008) [10.1109/NSSMIC.2008.4774694].
File in questo prodotto:
Non ci sono file associati a questo prodotto.

I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.

Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11589/20986
Citazioni
  • Scopus 10
  • ???jsp.display-item.citation.isi??? 0
social impact