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EnglishWe propose a novel CMOS baseline holder circuit, able to keep at a specified value the dc output voltage of typical integrated front-end analog channels coupled to silicon detectors, for both high energy physics and medical imaging applications. The circuit, together with the shaping filter, forms a slow feedback loop. A very low frequency pole is obtained in the feedback path, without using large capacitance values, by exploiting a circuit technique based on the properties of operational transconductance amplifiers. The huge time constant achievable with the proposed technique makes this solution suitable to be applied to high-gain front-end circuits, since the stability conditions can be easily fulfilled. Two different non- linearity effects are exploited to limit the baseline shift which occurs at high signal rates. The circuit has been designed in a standard CMOS 0.35μm technology and the first experimental results obtained from different prototypes show the effectiveness of the proposed solution.
| Autori: | ||
| Titolo: | A Novel Output Baseline Holder Circuit for CMOS Front-End Analog Channels | |
| Data di pubblicazione: | 2008 | |
| Nome del convegno: | IEEE Nuclear Science Symposium, 2008, NSS '08 | |
| ISBN: | 978-1-4244-2715-4 978-1-4244-2714-7 | |
| Digital Object Identifier (DOI): | http://dx.doi.org/10.1109/NSSMIC.2008.4774694 | |
| Appare nelle tipologie: | 4.1 Contributo in Atti di convegno |
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