A frequency quadrupler based on cascaded push-push frequency doublers is presented in this work. Push-push frequency doublers suffer from limited power efficiency and conversion gain, mainly due to second-harmonic feedback. Conventional harmonic reflectors minimize this undesired feedback introducing a common-mode second-harmonic resonance, at the price of increased area and reduced bandwidth. In this design the harmonic reflector is embedded into the input matching network, resulting in a more compact design. The coupling coefficient between the multiple windings of the transformer secondary is used to decouple the differential-mode inductance from the common-mode inductance, that acts as a wideband harmonic reflector. A common-gate transistor is stacked with the push-push pair to further boost the output power while reusing the same current. Two push-push frequency doublers are cascaded without additional power amplification stages. The quadrupler, implemented in 28nm CMOS, achieves a peak output power of 0 dBm and peak power efficiency of 5% at 77 GHz and the 3-dB bandwidth is from 70 to 86 GHz.
A Compact 70-86 GHz Bandwidth Frequency Quadrupler with Transformer-Based Harmonic Reflectors in 28nm CMOS / Ricco, P; Avitabile, G; Manstretta, D. - (2023), pp. 169-172. [10.1109/RFIC54547.2023.10186198]
A Compact 70-86 GHz Bandwidth Frequency Quadrupler with Transformer-Based Harmonic Reflectors in 28nm CMOS
Avitabile, GConceptualization
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2023-01-01
Abstract
A frequency quadrupler based on cascaded push-push frequency doublers is presented in this work. Push-push frequency doublers suffer from limited power efficiency and conversion gain, mainly due to second-harmonic feedback. Conventional harmonic reflectors minimize this undesired feedback introducing a common-mode second-harmonic resonance, at the price of increased area and reduced bandwidth. In this design the harmonic reflector is embedded into the input matching network, resulting in a more compact design. The coupling coefficient between the multiple windings of the transformer secondary is used to decouple the differential-mode inductance from the common-mode inductance, that acts as a wideband harmonic reflector. A common-gate transistor is stacked with the push-push pair to further boost the output power while reusing the same current. Two push-push frequency doublers are cascaded without additional power amplification stages. The quadrupler, implemented in 28nm CMOS, achieves a peak output power of 0 dBm and peak power efficiency of 5% at 77 GHz and the 3-dB bandwidth is from 70 to 86 GHz.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.