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Titolo Data di pubblicazione Autori File
DESIGN AND COST EVELUATION OF SIMPLE INTERCONNECTION CIRCUITS FOR MULTIPROCESSOR SYSTEMS 1-gen-1988 CORSI, FrancescoCAMARDA, PietroDi Lecce, Vincenzo +
A study of GaAs MESFET nonlinear models for circuit simulation 1-gen-1988 CORSI, FrancescoPERRI, Anna Gina +
Noise characterization of GaAs MESFETs for the design of optical amplifiers 1-gen-1988 CORSI, FrancescoPERRI, Anna Gina +
SPICE SIMULATION OF LATCH-UP ANOMALOUS EFFECTS OBSERVED BY ELECTRICAL MEASUREMENTS AND IR MICROSCOPY 1-gen-1988 CORSI, Francesco +
Design and Cost Evaluation of Simple Interconnection Circuits for Multiprocessor Systems 1-gen-1988 P. CamardaB. CastagnoloF. CorsiV. Di Lecce
PENELOPE: a graph based logic simulator for MOS circuits 1-gen-1988 Castagnolo, B.Corsi, F. +
CHARACTERIZATION OF ANOMALOUSLATCH-UP EFFECTS BY MEANS OF IR MICROSCOPY AND SPICE SIMULATION 1-gen-1988 CORSI, Francesco +
INFRARED MICROSCOPY DIRECT OBSERVATION OF CURRENTE REDISTRIBUTION AND SPICE SIMULATION OF LATCH-UP I-V HYSTERESIS EFFECTS 1-gen-1988 CORSI, Francesco +
CORRELATION BETWEEN ANOMALOUS LATCH-UP I-V CHARACTERISTICS AND OBSERVATION OF CURRENT DISTRIBUTION BY IR MICROSCOPY IN CMOS IC'S 1-gen-1988 CORSI, Francesco +
A COMPARISON OF CIRCUIT SIMULATION MODELS OF GAAS MESFETS BY EXPERIMENTAL CHARACTERIZATION 1-gen-1988 CORSI, FrancescoPERRI, Anna Gina +
ANALYTICA TECHNIQUESFOR LOCALIZATION AND SENSITIVITY ANALYSIS OF LATCH-UP IN CMOS IC'S 1-gen-1988 CORSI, Francesco +
Infrared microscopy study of anomalous latchup characteristics due to current redistribution in different parasitic paths 1-gen-1989 F. Corsi +
CORRELATION BETWEEN LATCH-UP HYSTERESIS AND WINDOW EFFECTS IN COMMERCIAL CMOS IC'S BY MEANS OF IR MICROSCOPY AND SCANNING LASER MICROSCOPY 1-gen-1989 CORSI, Francesco +
Noise characterization of GaAs MESFETs for the design of optical amplifiers 1-gen-1990 Perri, Anna G.Armenise, Mario N.Corsi, Francesco
VLSI reliability: Contributions from a three year national research program 1-gen-1990 Francesco Corsi +
Physical Defects vs Circuit Faults in a CMOS Programmable Logic Device 1-gen-1990 CORSI, FrancescoDE VENUTO, Daniela +
TEST GENERATION FOR PAL DEVICES 1-gen-1991 CORSI, Francesco +
THE USE OF A SWITCHABLE MEMORY TO ENHANCE THE PERFORMANCE OF A STRENGHTENED NODE 1-gen-1991 CORSI, Francesco +
IMPLEMENTING FINITE STATE MACHINES BY PROGRAMMABLE LOGIC DEVICES 1-gen-1991 CORSI, Francesco +
ACCURATE EVALUATION OF CRITICAL AREAS FOR SHORTS BETWEEN FINITE LENGHT CONDUCTORS 1-gen-1991 CORSI, FrancescoMARZOCCA C +
Mostrati risultati da 21 a 40 di 196
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